Senior Product Development Engineer
2 weeks ago
Drive Innovation at Cadence
Cadence Design Systems, Inc. is seeking a highly skilled Senior Product Development Engineer to join our dynamic IP team. This role offers a tremendous opportunity to work with an experienced team focusing on the development of best-in-class digital and mixed-signal IP products.
The ideal candidate will be a key member of technical staff in an organization responsible for IP activities, including pre-sales engagement with potential customers, pre-silicon integration, and post-silicon bring-up and test support for customers. The candidate will be the primary interface between customers and the CDNS R&D team, requiring strong communication skills and the ability to manage multiple priorities on a day-to-day basis.
Primary Responsibilities:
- Support integration, customization, and post-silicon bring-up of CDNS DDR IP subsystems.
- Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
- Support DDR PHY and controller SOC integration reviews and integration questions.
- Perform RTL and gate-level simulations to verify functionality.
- Assist customers with gate-level simulations and timing closure.
- Participate in the development of CDNS documentations and checklists for customers.
- Support post-silicon bring-up and deployment activities by our customers.
- Enhance customer experience by providing prompt updates to customers.
Position Requirements:
- M.S. Electrical/Computer Engineering (or similar degree).
- 3+ years of overall experience.
- Experience working with DDR4/5, LPDDR4/5 IP.
- Verilog RTL design and gate-level verification experience.
- Synthesis and STA experience, back-end experience is a plus.
- Familiarity with industry-standard DFT flows and test methodologies.
- Familiarity with package and board design.
- Ability to read schematics and participate in SI/PI reviews for customer board/package implementation.
Preferred Qualifications
- Experience with DDR PHY and DSP-based architectures.
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