ASIC Layout Engineer_BST

Are you ready to take on the role of ASIC layout designer? You'll be in charge of analog layout design from block level up to top level IC integration and physical verification for cutting-edge ASIC in MEMS sensor technology. Working closely with a global design team, you'll ensure timely and high-quality layout delivery, and collaborate on the tape-out process with the wafer foundry. Your teamwork with digital backend engineers to create DFE files for P&R and integrate digital layout into the entire chip will be crucial. Additionally, you'll partner with CAD engineers to enhance our PDKs and design environment continually.

• Hold a Bachelor's or Master's degree in microelectronics or a related electrical engineering field, with a focus on analog circuits, digital circuits, semiconductor devices and physics, and semiconductor manufacturing.
• Bring with you 5+ years of experience in analog/mixed-signal integrated circuit layout for components like ADCs, DACs, PLLs, LDOs, Charge pumps, and bandgap designs.
• Demonstrate a deep understanding of TSMC 28nm-152nm, SMIC 110nm, TZ 180nm BCD SOI technologies, and design rules.
• Possess a solid grasp of industry-standard IC layout practices and protocols to mitigate layout risks effectively.
• Have proficiency in tools like Cadence Virtuoso and verification/extraction tools from Cadence and Mentor Graphics (Calibre, PVS, Assura, etc.).
• Understand CMOS process-related challenges and know how to minimize risks in layout design (e.g., lithographic mismatch, LOD effect, WPE effect, latch-up, ESD, antenna, density stress, etc.).
• Capable of analyzing EM and IR drop issues.
• Skilled in operating the Linux system.
• Possess strong problem-solving abilities.
• Exhibit fluency in both written and spoken English.