Principal High Speed Clocking Design Engineer

6 days ago

Shenzhen, Guangdong, China Monolithic Power Systems Full time CN¥120,000 - CN¥240,000 per year

Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world ---come join our team and see how YOU can make a difference.

Job Description:

Summary:
The candidate will be part of the memory design team supporting the definition, specification, system simulation and implementation of future DDR, LPDDR related product IPs. The focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of specifications for the high-speed data path.

RESPONSIBILITIES:
1. This is a lead position where the designer will own the critical clocking blocks such as PLL, VCO, PI.
2. Ownership of high-speed analog/mixed signal designs at chip and block level
3. Design, simulate and characterize high-performance and high-speed circuits
4. Create high level model for design tradeoff analysis and behavior model for verification simulations
5. Work with digital/system teams to define architecture and design plan to achieve budget, schedule and project deliverable goal
6. Create floor plan and work with layout team to demonstrate post extraction performance
7. Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow
8. Work with the lab and system team for test plan, silicon bring-up and characterization
9. Understand and disseminate applicable standards and its relevance in a given project to team
10. Mentor junior designers
11. Participate and contribute to the definition of development flows that improve efficiency and quality of design execution

REQUIREMENTS:
1. MS EE and 7+ years or PhD EE and 5+ years' experience of analog/mixed-signal circuit design
2. Prior design experience in ultra-low noise PLL designs supporting sub-pico second high-frequency jitter (1UI, 2UI, 3UI) and random noise
3. Prior experience in ultra-noise, high-linearity, low-power PI architectures
4. Prior experience in memory clock tree designs
5. Knowledge of DDR5 specifications
6. Prior experience in DLL architectures a plus
7. Prior experience with data buffer architectures a plus
8. Prior experience with bandwidth peaking approaches a plus.
9. Solid knowledge of design principles for practical design tradeoffs
10. Solid knowledge of the basic building blocks like bias, op-amp and LDO
11. Experience in working in leading R&D and future technology development projects is desirable
12. Good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams

Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.

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