erc

Project: Tokenized Electric Vehicle Ecosystem and Real Estate We are currently partnered with a promising Real world asset tokenization team led by a licensed asset management group, tokenizing a diversified portfolio of income-generating electric vehicle ecosystem and real estate assets, bridging traditional finance and decentralized finance for global...

A pioneering Custom Tokenization-As-A-Service platform focused on Real-World Assets (RWA) is expanding its engineering team. Backed by strong angel investors and preparing for institutional funding, we partner with licensed exchanges and target Fortune 500 enterprises, AI data centers, and specialized sectors to bring enhanced liquidity and efficiency...

• Supports country SSU strategy in close collaboration with the SSO Study Start-Up Team Lead and the SSO Study Start-Up Managers to ensure SSU timelines and deliverables are met according to country commitments • Accountable for coordination, preparation, and execution of clinical study contracts and amendments (PI, site, institution, MSA, local vendors,...

该职位来源于猎聘 工作地点：上海 招聘对象：2027 届毕业生 薪资：12K~20K/M 岗位简介：加入模拟版图团队，参与电机控制/电源/混合信号芯片的定制版图设计与物理验证，在资深工程师带教下成长为模拟版图工程师。 培养与成长： 1....

工作职责1、主要负责IP版图工作， 包括DC-DC， LDO，OPA, ADC， DAC，PLL，高速SerDes，DDRIO, IO, Memory Compiler 等； 2、参与芯片版图的全流程设计，包括封装，布局，布线，验证，流片等； 3、负责芯片模块和顶层的版图设计，负责版图的验证，包括DRC，LVS， ANT，ERC，Power Plot，EM/IR...

工作职责工作职责 1、完成芯片的数字后端物理设计（Netlist to GDS...

工作职责1、完成芯片的数字后端物理设计（Netlist to GDS...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Custom Layout Design EngineerPosition Description:      Responsible for custom layout floorplan, matching guides, resistor/capacitor placement, reduce coupling & noise, sensitive signals routing, mix-signals routing, etc.Responsible for custom...

工作职责1. ASIC IC 设计芯片后端工程师从RTL2GDSII 2. 布局布线，电源网络设计，时序收敛，功耗分析，物理验证等 任职要求任职要求硕士学位，微电子，计算机相关专业 1. 具有复杂数字后端设计的RTL2GDS工作经验 2....

工作职责1、ASIC IC...

工作职责1、ASIC IC...

工作职责1、ASIC IC 芯片后端设计工程师从Netlist2GDSII 2、布局布线，电源网络设计，时序收敛，功耗分析，物理验证等任职要求1. 硕士学位，微电子，计算机相关专业，超过3年以上的芯片后端实践经验； 2. 具有复杂数字后端设计的Netlist2GDS工作经验； 3....

We are seeking a highly technical Senior QA Engineer to spearhead the quality assurance strategy for our client - Decentralized Exchange (DEX). This role focuses on the intersection of traditional exchange mechanics and blockchain technology, requiring a candidate who can perform deep white-box testing on smart contracts while ensuring the reliability of the...

该职位来源于猎聘 职位描述...

该职位来源于猎聘 职位描述...

Company DescriptionDo you want beneficial technologies being shaped your ideas? Whether in the areas of mobility solutions, consumer goods, industrial technology or energy and building technology - with us, you will have the chance to improve quality of life all across the globe. Welcome to Bosch.Job DescriptionAs an ASIC layout designer, you will be...

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Job DescriptionRole Overview Responsible for executing high-quality layouts across Standard Cells, I/O pads, and...

工作职责1、全芯片物理实现：负责从 Netlist 到 GDSII 的全芯片（Full Chip）顶层物理设计，包括布局规划（Floorplan）、电源网络设计（Power Grid）、自动布局布线（P&R）、时钟树综合（CTS）及布线优化。 2、先进工艺签核：基于 7nm/5nm/3nm...

该职位来源于猎聘 工作职责: 1. 根据电路和设计规则，独立完成模拟版图的设计和验证（DRC/LVS/ERC以及后仿提取 ），包括顶层布局布线、版图模块等； 2. 负责配合电路设计师优化版图达到指定的性能； 3. 撰写相关技术文档

**Company** Qualcomm China **Job Area** Interns Group, Interns Group > Interim Engineering Intern - SW **General Summary** - Handle synthesis/DFT logic insertion and ATPG pattern generation. - Handle physical design tasks from verilog netlist to GDS. - Handle Chip/Block floorplan, PD implementation, include placement, CTS,PCTS,routing,timing...