SW QA/Test Eng Intern

2 weeks ago

Shanghai, Shanghai, China Lattice Semiconductor Full time

Overview

There is energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for.

Responsibilities & Skills

This position is responsible for Lattice FPGA EDA Software being able to implement RTL design to Lattice FPGA device correctly and efficently. By studying FPGA architecture and the function of each IP, design RTL test case to verify EDA tools, Identify, analyze and locate the Software bugs to ensure EDA Software quality.

Responsibilities:

Verify the correctness of FPGA modeling for FPGA IP PLC, EBR, DSP, PLL, USB, JTAG and so on. Verify the functionality of synthesis tool, be able to infer EBR, DSP, Distributed RAM correctly. Verify the functionality of place and route, be able to implement netlist to FPGA resource correctly and effiently. Verify the functionality of static timing analyzer, be able to analyze timing path based on SDC constrains. Clean up customer CR cases and add into regression suites. Build up GUI Tools test case and clean up Squish test cases per request. Participate in lab machine maintainence and set up per request. Participate in QA regression testing activities, analyze the issues and report the issues per request.

Requirements:

Postgraduate/undergraduate student in Electronic information engineering, Automation Control, Electrical Engineering or relevant major. Has digital logic circuit knowledge, strong learning ability. Familar with Verilog, System Verilog or VHDL coding. Familar with FPGA application and EDA tools Modelsim are perferable. Experience in operation system Windows and Linux. Good written and verbal communication skills in English.

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