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Analog IC Layout Engineer

2 months ago

Shanghai, Shanghai, China Bosch Full time
Job Overview

As a Senior ASIC Layout Designer at Bosch, you will play a crucial role in the analog layout design process, overseeing tasks from block-level design to top-level IC integration and physical verification for cutting-edge ASICs in MEMS sensor technology. Collaborating with a global design team, you will ensure timely and high-quality layout deliveries, while managing the entire tape-out process in conjunction with wafer foundries.

Key Responsibilities

  • Collaborate with digital backend engineers to produce DFE files for place and route, integrating digital layouts into the overall chip architecture.
  • Partner with CAD engineers to enhance our process design kits (PDKs) and optimize the design environment.

Qualifications

  • A bachelor's or master's degree in microelectronics or a related field of electrical engineering, with a focus on analog circuits, digital circuits, semiconductor physics, and manufacturing.
  • A minimum of 5 years of experience in analog/mixed-signal integrated circuit layout, specifically for components such as ADCs, DACs, PLLs, LDOs, charge pumps, and bandgap references.
  • Extensive knowledge of TSMC 28nm to 152nm, SMIC 110nm, and TZ 180nm BCD SOI technologies, along with their respective design rules.
  • Strong understanding of industry-standard IC layout conventions aimed at minimizing layout risks.
  • Proficiency in the Cadence Virtuoso platform and familiarity with Cadence and Mentor Graphics verification and extraction tools (Calibre, PVS, Assura, etc.).
  • Awareness of CMOS process-related effects and strategies to mitigate layout risks, including lithographic mismatch, latch-up, ESD, and density stress.
  • Capability to analyze electromigration (EM) and IR drop issues.
  • Competence in using the Linux operating system.
  • Excellent problem-solving abilities.
  • Proficient in English, both written and spoken.